A High-Performance and Low-Cost FPGA-Based Accelerator for Singular Value Decomposition

FPGA-based floating-point singular value decomposition (SVD) faces significant challenges due to rapidly increasing matrix dimensions and stringent real-time requirements. Achieving high-performance SVD processors on low-cost FPGA platforms has become a critical research focus. Existing solutions suffer from imbalanced hardware resource utilization caused by insufficient parallelism or excessive pursuit of performance, failing to balance efficiency and economy. This paper proposes a novel time-division multiplexing rotation parameter computation method for Jacobi algorithm, which dynamically schedules and reuses computational modules to drastically reduce resource overhead of high-parallelism SVD processors. Additionally, a Distributed Computing Unit Communication Array tailored for FPGA is designed to enhance computational efficiency through compact data scheduling mechanisms. The architecture demonstrates strong scalability for diverse mid-to-low-cost FPGA platforms. Experimental results verify that the proposed SVD processor outperforms existing implementations in speed, hardware cost, and scalability. Compared with state-of-the-art counterparts, it achieves over 1.5× average speed improvement under identical hardware cost constraints.