VLSI Design and Implementation of Canonical Signed Digit-based Optimized FIR Filter Architecture

In this paper, the power-area-delay efficient hardware architecture of the Finite Impulse Response (FIR) filter is designed for signal processing applications. The multiplier is a complex module in the filter and hence it is replaced with the multiplierless design which consists of adders and shifters only. For this multiplierless design, the filter coefficients are denoted in Canonical Signed Digit (CSD) representation rather than the binary form. This CSD prunes the number of non-zero bits in coefficient representation and hence less number of adders needed. Due to the reduction of the adders, the multiplier will be improved in terms of area and power. The filter coefficients are generated for the specifications in MATLAB and The filter structure and CSD blocks are coded by Verilog HDL and synthesized using Xilinx Vivado tools. The real area, power and delay reports are produced in the Cadence environment by Genus tools in 45nm technology.