Development of Spurious Inverter based Level Shifter for Network on Chip Communication

The Power, delay and scaling efficiency of Networks-on Chip communication could be enhanced through the use of voltage Level Shifters (LS). The communication networks consist of a variety of circuit blocks and will be affected by a variety of LSs. The article presents a new development of Spurious Inverter Based Level shifter (IBLS) for network on chip communication with low delay and power. IBLS s designed using feedback topology that allows high data rate data transmission interconnections. The proposed IBLS used eight MOS transistors with low aspect ratios, which can be used to level both up and down. The resulting LS can shift between 0.2 V and 1.3 V, while delivering substantial decrease in power and delay. It's optimized for 45 nm CMOS node. Post-layout simulations prove the efficiency in the voltage transformation. It is found that the suggested LS is able to operate with an average of just 22 ns delay, and an energy consumption of 18 fJ while changing at 1 MHz signal. All high speed networks on chip applications can be implemented using IBLS.