Design and Implementation of a YOLOv4-tiny Hardware Accelerator with PYNQ-Z1

In this paper we design and implement an YOLOv4 tiny network hardware acceleration scheme based on Xilinx Zynq 7020 SOC chip following HLS approach. According to the characteristics of the network, different data transferring and caching techniques are adopted to implement different layers of the network. Experimental results on the PYNQ-Z1 development board show that the design achieves a computational performance of 42.18 GOPS with an energy efficiency ratio of 9.6 GOPS/W and an inference response time of 165 ms.