Optimized Low-Power Lossless ECG Compression for Healthcare Monitoring Systems

Electrocardiogram (ECG) signal compression is essential for reducing storage requirements and transmission bandwidth in modern healthcare applications. This work introduces a novel dual-mode prediction and transform coding framework for ECG compression, achieving a superior lossless bit compression ratio of 3.869, outperforming existing methods. The proposed design is optimized for low-power applications, featuring a significant reduction in gate count, power consumption, and core area. The hardware implementation comprises 115 Basic Elements of Logic Systems (BELS), 33 Flip-Flops and latches, 1 clock buffer, and 34 IO buffers, ensuring minimal resource utilization. The proposed Very Large Scale Integration (VLSI) architecture is highly efficient for real-time healthcare monitoring systems, achieving a compact cell area of 1303.382 with a total cell count of 137. Additionally, the core chip operates at an ultra-low power consumption of 0.56 mW, making it highly suitable for energy-constrained wearable and embedded healthcare devices. The design is implemented and validated using Xilinx tools and 90nm CMOS technology. The results demonstrate that our innovative approach provides a power-efficient and area-optimized solution for ECG signal processing, offering a significant advancement in low-power biomedical signal compression.