A Compact D-Band Phase Shifter With 0.1-Degree Phase Resolution and Ultra-Low Phase Error in 65-nm CMOS

This article introduces a compact D-band phase shifter, which achieves high-resolution phase steps and ultra-low phase error, designed for the sixth-generation (6G) mobile network. The proposed design integrates two novel circuit architectures: a feedback fine-tuning phase shifter (FFPS) provides precise phase control with fine 0.1° steps over a 22.5° range by using a feedback transmission line (TL) to enhance gain and tuning range. The second architecture is a two-mode non-uniform propagation delay phase shifter (2-mode NU-PDPS), which enables coarse phase tuning with 22.5° steps, covering a full 360° phase range. It employs non-uniform MOSFET sizing to realize ideal TL operation. In addition, two modes are introduced in the quarter-wave TL to increase phase resolution without increasing area and thus achieves a core area of 0.06<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {mm}^{2}$</tex-math> </inline-formula>. The proposed phase shifter operates with 0.1° steps over a 360° fine-tuning range within the frequency range of 150–160 GHz. It achieves an rms phase error of 0.68°, the lowest among reported phase shifters in this frequency range. The total power consumption is 5mW at 1.0-V VDD, with an insertion loss of −2.5dB.