Enhancing Program Speed and Diminishing Read After Write Delay by Metal Work Function Engineering

We investigate the impact of gate metal work function (Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub>) engineering on the performance of Metal - Interlayer – Ferroelectric (FE) – Interlayer – Silicon (MIFIS) ferroelectric field effect transistors (FeFET). The gate injected trapped charge (Q<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</sub>’) plays a critical role in determining key device parameters such as the memory window (MW) and operating voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">op</sub>), making Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> optimization a viable approach to enhance MIFIS FeFET performance. To evaluate this effect, we fabricated devices with Al (Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> = 4.1 eV), TiN (Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> = 4.7 eV), Pt (Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> = 5.35 eV) gate metals. A higher Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> reduces the valence band offset at the gate interlayer (G.IL), facilitating hole injection during program (PGM) operations. This results in a lower PGM V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">op</sub> and a steeper incremental step pulse programming (ISPP) profile. Simulation results confirm that enhanced gate hole injection underpins the observed ISPP behavior. Additionally, high Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> gates reduce read after write delay (RAWD) and lower de-trap pulse amplitudes. Our findings establish gate Ф<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> engineering as an effective strategy to improve MIFIS FeFET performance, particularly for low-voltage operation and disturbance mitigation.