A method for fabricating CMOS back-end-of-line-compatible solid-state nanopore devices

Solid-state nanopores (ssNPs), nm-sized holes in thin, freestanding membranes, are powerful single-molecule sensors capable of interrogating a wide range of target analytes, from small molecules to large polymers. Interestingly, due to their high spatial resolution, nanopores can also identify tags on long polymers, making them an attractive option as the reading element for molecular information storage strategies. To fully leverage the compact and robust nature of ssNPs, however, they will need to be packaged in a highly parallelized manner with on-chip electronic signal processing capabilities to rapidly and accurately handle the data generated. Additionally, the membrane itself must have specific physical, chemical, and electrical properties to ensure sufficient signal-to-noise ratios are achieved, with the traditional membrane material being SiN<i>_x</i>. Unfortunately, the typical method of deposition, low-pressure vapour deposition, requires temperatures beyond the thermal budget of complementary metal-oxide semiconductor back-end-of-line (BEOL) integration processes, limiting the potential to generate an on-chip solution. To this end, we explore various lower-temperature deposition techniques that are BEOL-compatible to generate SiN<i>_x</i>membranes for ssNP use, and successfully demonstrate the ability for these alternative methods to generate low-noise nanopores that are capable of performing single-molecule experiments.