High reliable fast write with boosted word line low leakage power and energy efficient 12T SRAM cell

Abstract As modern SRAM architectures face increasing demands for high performance and energy efficiency, the proposed 12T SRAM cell offers substantial improvements over conventional designs. This architecture integrates a dynamic word line boosting technique during write operations, significantly enhancing write speed while reducing energy consumption. A data dependent supply voltage scheme further optimizes power efficiency by adjusting the supply voltage based on stored data. To minimize static power and leakage, the design employs several low-power techniques, including high-threshold voltage (HVT) transistors, transistor stacking, and ground gating. A read buffer is incorporated to improve read stability without the overhead of an additional bit line. Simulation results demonstrate that the static power consumption of consider SRAM cells 11T, 10T, 12T_SRL, 12T_ST, 8T, and 6T is 1.27 × , 3.38 × , 1.87 × , 2.96 × , 5.81 × , and 5.67 × higher, respectively, compared to the proposed 12T design. Furthermore, the Write Static Noise Margin (WSNM) of these cells is found to be 1.53 × , 1.57 × , 2.23 × , 2.23 × , 1.96 × , and 1.96 × lower, respectively. Additionally, we proposed 12Tcell with boosted word line. The proposed 12T with boosted word line achieves the highest WSNM and demonstrates the lowest read and write energy consumption compared to all consider cell with least static power dissipation making it highly suitable for low-power, high-reliability memory applications.