A 5.8-GHz 4.8-mW −247.1dB-FoM DTC-Free Sampling ΔΣ Fractional-N PLL With Embedded Phase Interpolation

This paper presents a sampling fractional-N PLL employing phase interpolation embedded within linear slope generator (LSG), obviating the need for a digital-to-time converter (DTC) and RF time-domain phase interpolation (PI). Thus, the phase dithering can be achieved with only a quad-phase divider and LSG to synthesize fractional-N frequencies. By realizing large phase detector (PD) gain through the proposed architecture, it achieves an in-band phase noise of -110.4 dBc/Hz and reference spur of -74 dBc/Hz. Fabricated in 65-nm CMOS, the 5.7 5.9 GHz PLL achieves -247.1 dB FOM with 4.8-mW power consumption.