Machine Learning-Based Leakage Prediction in Analog Logic Gates under PVT Variations

Traditional SPICE-based simulations are accurate but computationally expensive for modeling leakage behavior in analog logic circuits under large-scale process, voltage, and temperature (PVT) variations. This paper proposes a machine learning-based approach to predict leakage in multiple logic gate structures, significantly reducing the simulation time while maintaining high accuracy. We evaluate a variety of models including linear, non-linear, and deep learning methods, and explore the impact of feature correlations and multicollinearity. The Decision Tree model, selected for its optimal trade-off between accuracy, training time, and model size, achieves a mean absolute percentage error (MAPE) of 0.032 and an R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> value above 0.97 across all test circuits. Additionally, SHAP analysis provides interpretability, revealing key factors influencing leakage behavior. Our approach offers a reliable, efficient alternative for leakage prediction in analog circuit design under varying operational conditions.