Design and implementation of FinFET and GnrFET based nano arithmetic logic unit

• Arithmetic units like adders, and subtractors are basic components in many integrated circuits including arithmetic logic units (ALUs), microprocessors, and micro controllers. However, the use of complementary metal oxide semiconductor (CMOS) and field effect transistor (FET) technologies in the production of conventional adders, and subtractors led to a rise in the total transistor count and a subsequent increase in power consumption. • So, the initial focus of this work is on the creation of hybrid adder-subtractor designs based on FinFET and graphene nano-ribbon field effect transistors (GnrFET) nano technologies. The initial development is enhanced full adder with carry prediction (EFOCP) based on multiplexer logic, featuring rapid selection of carry-outputs, resulted in a significant reduction in delays caused by sum estimation. • This result was achieved because of the significant reduction in the amount of time it took to select carry-outputs. By utilizing the EFOCP module to select the high-speed and low-speed carry propagation channels, dynamic path auto-configurable adder (DPAA). An Arithmetic Logic Unit (ALU) is a fundamental digital circuit within a central processing unit (CPU) or microprocessor that performs arithmetic and logical operations on binary data. However, the conventional complementary metal oxide semiconductor (CMOS) based ALUs were consumed a greater number of transistors, power, and delay consumptions. So, this work focused on development of nanotechnology based ALU (Nano-ALU) using Fin field effect transistors (FinFET) and graphene nano-ribbon field effect transistors (GnrFET). Initially, the dynamic path auto-configurable joint-adder-subtractor (DPAJAS) is developed by using multiplexer path selectable full adder (MPFA), enhanced full adder with carry prediction (EFOCP) modules. Then, the dynamic path auto-configurable multiplier is (DPAM) is developed by adopting redundant booth encoding (RBE) and dynamic path auto-configurable adder (DPAA) property of DPAJAS, which contains the multiplexer logics to perform fast switching of data. Finally, the Nano-ALU developed by combining the DPAJAS, DPAM modules, and logical operations. The proposed Nano-ALU outperforms the compared traditional ALUs with an average reduction of approximately 15.7 % in Total Energy Consumption (TEC), about 14.6 % in Total Path Delay (TPD), approximately 15.3 % in Carry Out Rise Delay (CORD), roughly 13.2 % in Carry Out Fall Delay (COFD), approximately 11.0 % in Sum Rise Delay (SRD), about 11.0 % in Sum Fall Delay (SFD), and approximately 6.3 % in Average Power Consumption (APC).