Research into the Properties of Modular Weight-Based Sum Codes in Concurrent Error-Detection Circuits Based on Boolean Signals Correction

This paper describes the design principles of modular weight-based sum codes, focusing primarily on cases with m = 5 data symbols and M = 4, 8, 16, 32, 64 modulus values. The total number of variants with a sequence of weighting coefficient and the number of those providing uniform distribution of data vectors between check vectors have been determined for each code class considered. The conditions for selecting weighting coefficients that ensure a uniform distribution have been formulated. An algorithm for synthesizing the concurrent error-detection circuit with Boolean signals correction has been proposed, as well as the structure of the concurrent error-detection circuit with correction of signals forming check symbols of the modular weight-based sum code. The structure has been generalized for the code with m = 5 data symbols. Experimental studies have been carried out on a set of MCNC Benchmarks, demonstrating that the proposed method significantly reduces the complexity of device implementation in comparison with the duplication method. The research results confirm the high flexibility of the proposed approach and its promising potential for designing selfchecking digital devices