Design Of Low Power Eight Bit Signed Wallace Tree Multiplier For FIR Filter

In VLSI design, minimizing power consumption is a critical objective, especially for multiplier circuits widely used in applications such as digital filtering, communication systems, and spectral analysis. This project presents the design of an 8-bit signed multiplier using Cadence Virtuoso, a powerful tool for circuit design and simulation. The proposed architecture utilizes a 4T-XOR-based full adder to significantly reduce transistor count, leading to improved energy efficiency. Hybrid full and half adders are arranged in an adder tree structure to efficiently sum partial products generated by AND gates, producing a 16-bit output optimized for low power. The proposed multiplier design achieves an average power consumption of 1.89 mW. Cadence Virtuoso enables detailed power analysis of the design and its components in 45nm Technology, ensuring energy efficiency across varying conditions. This work addresses the critical challenge of low-power design in VLSI, delivering an efficient multiplier suitable for modern digital systems.