Low Power Approximate Full Adders Using GNRFET

The increasing need for low-power consumption in contemporary digital systems, particularly for energy-sensitive and battery-powered applications, has driven the adoption of approximate computing. This approach permits controlled inaccuracies to achieve reduced power usage, making it highly suitable for domains like machine learning and multimedia processing. Approximate full adders play a key role in this method, offering a balance between accuracy and energy efficiency, making them essential for creating low-power designs. GNRFETs at the 16 nm node have emerged as a promising alternative to CMOS and FinFET technologies, offering advantages such as reduced leakage currents, high carrier mobility, and enhanced electrostatic control, ensuring efficient nanoscale performance. This research introduces a 12T GNRFET-based full adder with an error propagation mechanism, achieving a 49% decrease in static power and significant improvements in power-delay and energy-delay products. Simulation results, obtained using an 8-bit adder optimized through Synopsys HSPICE, demonstrate the potential of GNRFET technology for developing energy-efficient digital circuits.