Handwritten Digit Recognition Using Low Latency Convolutional Neural Network Architecture

Convolutional Neural Networks (CNNs), a specialized type of feed-forward deep neural network, are widely used for efficient and accurate image recognition, playing a crucial role in various Artificial Intelligence applications. To meet the growing demand for low-power and area-efficient hardware accelerators, Field Programmable Gate Arrays (FPGAs) emerge as an ideal solution due to their high parallel processing capabilities, low power consumption, and remarkable flexibility. This work aims to implement a CNN architecture on an FPGA for handwritten digit recognition, achieving faster computation, low latency, and high accuracy. Techniques such as multi-input processing, zero pruning, maximum finder for dense layers, fixed-point multiplication, row-stationary methods for feature extraction, and pipelining with parallel processing are employed to enhance performance. The proposed design is implemented on a Xilinx Zynq-7000 FPGA and evaluated using the MNIST dataset. Experimental results demonstrate a 65% reduction in clock cycles for the feed-forward network and a 75% reduction for the convolutional network compared to existing systems.