Toward Wafer-Scale Screening of Spin Qubits: A Room-Temperature-Aware Single-Electron Transistor Design

Testing of spin-based quantum devices is currently performed through quantum dot and qubit measurements at deep cryogenic temperatures, well below 1 K. At such low temperatures, the testing throughput is strongly limited due to the long cool-down times and due to the large number of connections required between the device at deep-cryogenic temperature and the room-temperature control electronics. As the number of qubits in a single chip increases and as we advance toward large-scale manufacturing, developing effective techniques that allow to screen those chips at higher temperatures, possibly even room temperature, becomes indispensable. Transistor metrics constitute a promising indicator to identify, at room temperature, which devices are functional and also at cryogenic temperatures. Prior work has demonstrated a strong correlation between quantum dot metrics measured at deep-cryogenic temperature and transistor metrics up to 77 K. To ensure that such a correlation extends up to room temperature, electrostatic confinement of the conductive channel needs to be guaranteed. In this article, we propose a single-electron transistor (SET) design intended for the correlation study of transistor metrics from deep-cryogenic up to room temperatures. Our calibrated technology computer-aided design (TCAD) simulation results demonstrate the drastic improvement of the room-temperature transistor behavior of the proposed design, without the employment of physical device isolation that would negatively impact the qubit’s fidelity. In addition, this work presents a room-temperature-aware methodology in the design phase of spin-based devices, with promising scalability to structures containing a larger number of qubits.