A 45-nW 10-b 20-kS/s SAR ADC Based on Single-Capacitor Switching Scheme in 180-nm CMOS

This work presents a 10-bit 20-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a proposed single-capacitor switching scheme. Based on behavioral-level simulations and prototype chip testing, ultralow-power operation and significant chip area reduction are achieved. This novel switching scheme employs voltage level shifting instead of charge redistribution for the two most significant bit (MSB) decisions, thus eliminating switching power consumption. For the remaining bit decision, the technique minimizes reference voltage transitions while involving only a single capacitor in each switching. By employing the proposed switching scheme, the capacitance spread of capacitive digital-to-analog converter (CDAC) is reduced from conventional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{n-1}$</tex-math> </inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{n-3}$</tex-math> </inline-formula>, which reduces the CDAC area, relaxes capacitor matching requirements, and improves matching linearity. A prototype of the proposed ADC was designed and fabricated in SMIC 180-nm CMOS technology. The chip operates with a 0.6-V supply voltage and consumes 45-nW power at a sampling rate of 20 kS/s. The measurement results also show the signal-to-noise and distortion ratio (SNDR) of 56.4 dB, the spurious-free dynamic range (SFDR) of 70.4 dB, and the ENOB of 9.26 are achieved. The ADC occupies an area of only 0.063 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and attains the Walden figure of merit of 5.06 fJ/conversion-step at the Nyquist rate.