Reduced ΔCTE and Galvanic Corrosion Failures in Mass Production by Using a Robust Design for Medium to Large Display Panels

Flat panel displays for large applications (monitors and TVs) have structural weaknesses in improving the yield of mass-produced products due to large panels: the yield is defined by ratio of output quantity to input into panel fabrication process. From a panel manufacturing point of view, low-cost production should be achieved through improved yield of mass production (Samsung Display’s quantum dot display backplane panel). So, we set the target yield at an extreme value, over the golden yield (90%) at the beginning of new mass products. The main factors contributing to the yield loss were “lifted insulator and etched active pattern defects”. To reach the target yield, we focused on these two main defects. The root causes of these defects (delta coefficient of thermal expansion and galvanic corrosion) are explained, and a defect generation mechanism is proposed (the size of the separated large power line in relation to the defect rate). The power lines are defined based on an Electroluminescent Voltage at the Drain (ELVDD) and Electroluminescent Voltage at the Source (ELVSS). We developed a separated large power line design to reduce defect rates. This design plays a role in preventing these two defects during the mass production of medium to large display panels for use in TVs by ensuring that the large power line area is less than the optimum value (<0.44 cm2).