A Cost–Benefit Analysis of Multi-Site Wafer Testing

Wafer testing is a crucial process used to test dies before packaging. In recent years, the process has undergone significant changes to reduce costs and ensure sufficient test coverage while preserving ATE and die integrity. The process is associated with substantial expenses and consumes considerable time. In this paper, we aim to provide an overview of the current state of wafer testing and highlight the most critical aspects of this type of testing. This paper will discuss the direction of the industry in this sector by highlighting the potential critical issues introduced by the current technological limits when implementing future technologies such as denser pad layout and multi-site testing. The results of our work will consider the area occupation of the probe head, the number of springs, the multi-site wafer testing approach, and the pad layout on a die. To evaluate the impact of choices such as the choice of pitch and ratio, and the use of technologies such as the arrangement of matrix pads or the use of multi-site probe heads as precisely as possible, a dedicated tool has been developed and used for the calculation of new metrics and indices, such as the horizon, and all the graphs reported in this work.

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Publication Details

Journal
Electronics
Published
2025-06-16
DOI
https://doi.org/10.3390/electronics14122450
Citations
2
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
1.46
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article

A Cost–Benefit Analysis of Multi-Site Wafer Testing

Tommaso Foscale, Paolo Bernardi
2 citations
Electronics
3D IC and TSV technologies
1.46
article

A Cost–Benefit Analysis of Multi-Site Wafer Testing

Tommaso Foscale, Paolo Bernardi
article en
2 citations

Abstract

Wafer testing is a crucial process used to test dies before packaging. In recent years, the process has undergone significant changes to reduce costs and ensure sufficient test coverage while preserving ATE and die integrity. The process is associated with substantial expenses and consumes considerable time. In this paper, we aim to provide an overview of the current state of wafer testing and highlight the most critical aspects of this type of testing. This paper will discuss the direction of the industry in this sector by highlighting the potential critical issues introduced by the current technological limits when implementing future technologies such as denser pad layout and multi-site testing. The results of our work will consider the area occupation of the probe head, the number of springs, the multi-site wafer testing approach, and the pad layout on a die. To evaluate the impact of choices such as the choice of pitch and ratio, and the use of technologies such as the arrangement of matrix pads or the use of multi-site probe heads as precisely as possible, a dedicated tool has been developed and used for the calculation of new metrics and indices, such as the horizon, and all the graphs reported in this work.

ElectronicsVol. 14(12)
Politecnico di Torino (IT)
Openalex Percentile: Top 17%
3D IC and TSV technologies
1.46
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