Improved polishing process for silicon wafers in semiconductor manufacturing

There is a continuous need to improve semiconductor device performance through higher integration, which requires silicon wafers to be highly flat. In the double-sided polishing process, the flatness deteriorates due to nonuniformity of material removal. Therefore, wafers and consumables such as slurry and polishing pads are wasted due to repeated dummy processes to find as good process conditions as possible. The edges have poor flatness due to the roll-off shape and are wasted as Edge Exclusion area that cannot be used for chip manufacturing. To eliminate such waste and improve sustainability, it is necessary to develop a polishing process that does not deteriorate the surface flatness. This study established a polishing pad design for uniform removal distribution. An approach for improving the edge flatness was proposed by examining the effects of the initial edge shape and contact state between the wafer and polishing pad on the removal distribution.