Improved Ripple Carry Adder with Reduced Delay and Low Power Consumption at Circuit Level using 180 nm Technology

Abstract Full adder (FA) is a crucial building block in very-large-scale integration and digital signal processing applications, serving as a versatile component for addition, multiplication, arithmetic logic unit construction, etc. Its importance necessitates the development of an efficient adder block. To achieve high speed and low power consumption, various approaches can be employed. This study aims to implement a 4-bit ripple carry adder (RCA) using conventional, Boolean simplification, Boolean simplification with transistor sizing, and modified-gate diffusion input (m-GDI) logic in Cadence Virtuoso® software, based on Silterra 180 nm technology. The study aims to compare and analyze different techniques for reducing latency and power consumption in 4-bit RCA circuits, particularly using Boolean simplification, Boolean simplification with transistor sizing and m-GDI. The following four 1-bit FAs are considered: Basic FA (FA_1), Boolean simplified FA (FA_2), Boolean simplified with transistor sizing FA (FA_3), and m-GDI FA (FA_4). These FAs are evaluated and analyzed for delay and power consumption. Furthermore, the design of the four 1-bit FAs is integrated into a 4-bit RCA, and its impact on large-scale design is examined. The results indicate that the m-GDI 4-bit RCA (4bit_FA_4) exhibits optimized performance in terms of power consumption and propagation delay. It consumes 285.4 nW of power and achieves the best performance with a propagation delay of 118.845 ps.