A 1.6 μW 65nm CMOS Ultra-Low Noise Parallel Active Load OTA for Sensor Applications

Abstract This paper presents the design of an ultra-low power, ultra-low-noise paralle active load operational transconductance amplifier (PAL-OTA) in a 65 nm CMOS process, dissipating only 1.6 μW. The proposed design employs a singlestage differential pair configuration with a parallel active load, operating at a 0.8V supply voltage. The parallel active load increases the effective gate width, reducing flicker noise and contributing to the overall noise performance of the OTA, achieving an exceptionally low input-referred noise of 179.8 pV/√Hz. Simulation results demonstrate that the design achieves a favourable trade-off between power consumption, noise performance, and gain. The use of an active load significantly enhances the amplifier’s stability, increasing the phase margin from 80° to 90°. This makes the OTA particularly well-suited for ultra-low power analog systems.