A Triristor With Tri-Stable States Using Double Latches

A tri-stable resistor (triristor), structurally identical to a MOSFET built on a bulk silicon wafer, is demonstrated using double latches arising from single transistor latch (STL). It has two spatially and voltage-separated STL events: the first latch and second latch. Each causes an abrupt transition between current levels, providing a stable state in between. The first latch, occurring at a moderate drain voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub>), begins with bulk punchthrough current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulk,punch</sub>) flowing through the lightly doped body and triggers the first impact ionization (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">II</i>). The second latch, triggered at a higher <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub>, starts with surface subthreshold current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">surf,subth</sub>) near the Si-SiO2 interface, leading to the second <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">II</i>. These double latches result in tri-stable states, making the triristor applicable to ternary logic, and multi-valued memory as well as other innovative applications.