An energy-efficient digital computing-in-memory STT-MRAM macro for AdderNets with optimized addition operations

Adder neural networks (AdderNets), a promising lightweight alternative to traditional CNNs, face the “memory wall” challenge in von-Neumann architectures. Computing-in-memory (CIM) has emerged as a promising solution to address this memory bottleneck. This work proposes a novel spin-transfer torque magnetic random-access memory based digital-CIM macro tailored for AdderNets mapping, leveraging Boolean logic-optimized architecture to seamlessly integrate storage and computation. The architecture is validated through simulations under 40 nm CMOS technology. Results show that the architecture achieves an energy efficiency of 39.48 TOPS/W in 8-bit network inference, representing a 1.4× to 2.0× improvement over state-of-the-art digital CIM designs.