Wafer Scale Assessment of Dislocation Defects on SiC WafersUsing a Convolutional Neural Network

Abstract Wide bandgap semiconductors, such as SiC, are expected to surpass traditional
silicon-based technologies in high-power electronics applications, owing to their potential for
reduced size, weight, and enhanced power e ciency. SiC, in particular, has evolved signi cantly,
reaching a maturity that enables its use in high-voltage applications including power modules.
However, the current state-of-the-art SiC epitaxial wafers face signi cant challenges, primarily
due to the presence of threading dislocations, basal plane dislocations, stacking faults, polytype
inclusions, and screw dislocations. These structural imperfections lead to electron and hole carrier
scattering, which impairs device performance. Addressing this, the present research introduces a
novel approach employing a convolutional neural network (CNN) trained to identify and quantify
dislocation defects with high precision. Analysis of the models shows it is both highlighting the
features of interest and is de ning the shape, size, and number of the dislocations with higher
accuracy than the manual labeling used to train the model, suggesting that CNN has successfully
captured the subtle details needed to identify dislocations defects.