Accelerating Urban Traffic Management via FPGA-Based FSM Architecture

Abstract This paper presents the design and implementation of a traffic controller system on a Digilent Basys 3 FPGA board using Verilog Hardware Description Language (HDL). The system manages traffic light sequences at a four-way intersection, employing a Moore finite state machine to ensure deterministic transitions between green, yellow, and red states for North-South and East-West roads. Pushbuttons simulate car detection sensors, while timers control light durations (30 s green, 5 s yel- low, 2 s red). Implemented on the Xilinx Artix-7 FPGA, the design leverages parallel processing for real-time control, offering advantages over microcontroller-based systems in speed and reconfig- urability [1, 2]. The system was synthesized and simulated using Xilinx Vivado 2022.1, achieving a maximum operating frequency of 100 MHz, 25% LUT utilization, and 0.45 W power consumption. Simulation waveforms confirm accurate state transitions and sensor responsiveness. Resource uti- lization, timing analysis, and power consumption metrics demonstrate the design’s efficiency, with 8320 LUTs and 5400 flip-flops used, supporting scalability for complex intersections [3, 4]. The proposed controller provides a cost-effective, scalable solution for urban traffic management, with potential applications in smart city infrastructure [5]. This work contributes to electronics engi- neering by showcasing FPGA-based digital design for practical control systems, highlighting low power consumption and high performance. Future enhancements include integrating real-time sen- sors and adaptive timing algorithms to optimize traffic flow [6]. The design’s reconfigurability makes it adaptable to diverse traffic scenarios, advancing digital electronics applications. Keywords: FPGA, Traffic Controller, Verilog HDL, Basys 3, Moore State Machine, Digital Design