Improving Processing-In-Memory Chip Inferencing Accuracy Through Noise-Aware Training

The increasing demand for high-performance and energy-efficient neural network (NN) deployments has led to the adoption of Processing-In-Memory (PIM) architectures. While PIM offers significant advantages in speed, power consumption, and cost, its inherent analog noise introduces accuracy loss, limiting its application in accuracy-sensitive tasks. In this study, we propose a noise-aware training (NAT) method to address this challenge. By incorporating uniformly distributed noise, modeled from real PIM chip behavior, into the training process, NAT adapts neural networks to the error characteristics of PIM chips. Experimental results on a keyword recognition task demonstrate that NAT significantly reduces accuracy loss during PIM chip inference without degrading the model's intrinsic FP32 accuracy. Compared to both baseline training and quantization-aware training (QAT), NAT exhibits superior robustness to noise and achieves higher inference accuracy on PIM chips. These findings highlight the potential of NAT to enhance the reliability of PIM architectures, paving the way for their broader adoption in real-world applications.