Network-on-Chip Research Project Report

In order to break through the bandwidth and delay of data transmission, people have turned their attention to the on-chip network. Because it can meet the performance requirements of modern applications. This paper makes a new contribution to network on chip. For example, the router, routing algorithm, virtual channel allocation, input unit and state module are fully introduced and analyzed. The introduction content is explained in a combination of text and pictures in order to better understand the status and role of each module. The analysis includes a detailed explanation of the verilog language in key parts to help understand the signal flow direction and the system regulation role played by the control signal, as well as the tracking of the signal flow, studying how it carries information between multiple modules, and what signals will be in each shuttle to ensure the correctness of the signal flow direction. Then, the signal is simulated by software and the correctness and reliability of NoC-Verilog-master is verified successfully. The fact proves that this is a correct and reliable NoC system. Finally, the paper boldly proposes the challenges that NoC may face in the future, and makes a summary.