Design and Linearization of a Doherty Power Amplifier in 45 nm CMOS Technology for 5G Applications

Abstract Linearity and efficiency are simultaneously two important aspects for designing a power amplifier (PA) dedicated to 5G millimeter-wave applications. However, a PA suffers a trade-off between these two aspects. The maximum efficiency of this circuit happens in a non-linear region, which is not suited for mobile transmission applications. Besides, even when operating at the linear region, the circuit may not be able to fully comply with digital metrics standards which ensure a good quality for mobile transmission applications. To enhance efficiency in back-off regions from the PA non-linear region, Doherty topology is a good preference. To comply with digital metrics standards, enhancement of PA linearity through digital pre-distortion (DPD) is possible. This work presents the design of a Doherty PA at a central frequency of 26 GHz and focuses on showing a methodology for linearization with DPD using an iteration between SpectreRF and MATLAB. The PA is designed in a 45 nm node using a commercial CMOS process. DPD is applied using a memory polynomial model with an indirect learning structure to enhance its accuracy. For continuous-wave signals, the Doherty PA achieves a saturation power of 22.2 dBm, a peak PAE of 23.76% and 12.6% in 6 dB back-off region. DPD is applied to comply with error vector magnitude (EVM) standards for a 5G NR modulated signal. The DPD technique improves the linearity of the PA as it can be seen by the improvement in the measured EVM by 20/3 dB and in adjacent-channel-power-ratio (ACPR) by 18.36/4.28 dB for a 5G NR 256 QAM signal with 50/100 MHz bandwidth.