Reliably In‐Memory Ternary Stateful Logic Computing Based on Tri‐State Memristors with High On/Off Ratio

Abstract To surpass the slowdown of Moore's Law, multi‐valued logic (MVL) systems are explored to increase information processing density and enhance computational efficiency. Although conventional MVL systems offer substantial reductions in the number of devices and the circuit complexity, they still suffer the memory/power wall derived from the von Neumann architecture. Memristors have the potential to construct stateful logic circuits with in‐memory computing abilities which would further improve the computing efficiency by addressing the issues. In this paper, a tri‐state memristor based on the Ag/Al 2 O 3 /Ta 2 O 5 /Pt structure is introduced to in‐memory ternary stateful logic circuits. The stepped I–V behavior and device characteristics (a two‐order‐of‐magnitude on/off ratio between adjacent resistance states with endurance up to 10 4 ) ensure the experimental implementations of the ternary logic gates of three kinds of NOT, NAND, and NOR in the same circuit structure, which can be further extended to other 116 ternary logic gates. In addition, after settling the crosstalk issues, a decoder function is experimentally demonstrated by cascading ternary NOT gates and NOR gate to exhibit the in‐memory cascading characteristic of the proposed stateful logic circuits. This technology rooted in in‐memory computing and MVL systems offers more efficient solutions for future computer information processing endeavors.