Research and design of a matrix multiplier on FPGA

This paper presents a comprehensive investi- gation and hardware implementation of a multi-bit Brawn matrix multiplier architecture. The research focuses on analyzing the system characteristics of binary multipliers realized with both conventional and optimized full and half adders. Particular attention has been given to the applicability of such multipliers within arithmetic logic units (ALUs) for vector and scalar processing architectures. Analytical models have been formulated to quantify hardware resource utilization and computational latency across various logic base configurations. The proposed multiplier has been described using the VHDL hardware description language and validated through functional simulation. The designs have been synthesized and implemented on Xilinx FPGA platforms. It has been established that the use of improved full and partial binary adders as part of the Brown matrix multiplier reduces the hardware complexity by a factor of 1,7 and increases the performance by a factor of 2,9 compared to the known classical structures of binary adders. The use of multibit Brown matrix multipliers with an improved element base allows to significantly speed up the execution time of the multiplication operation of special-purpose processors and vector and scalar supercomputers.