A Novel 3D Stacked Vertical-Channel High-Voltage Peripheral Transistor for Largely Scaled the WL Driver Circuit of 1000-layer 3D NAND Flash

3D NAND technology is expected to continue advancing toward 1000-layer stacking in pursuit of ever-higher memory density per chip [1]. However, increasing the number of layers presents significant challenges, not only in array stacking but also in the design of the wordline (WL) driver circuits. Each WL requires an independent high-voltage (HV) pass-gate transistor for array operations, and the linear increase in the number of layers directly enlarges the WL driver circuit area, leading to reduced array layout efficiency. In this paper, we propose a novel vertical-channel gate-all-around (GAA) HV transistor. This device leverages the existing 3D NAND Flash manufacturing process, integrated with conventional planar CMOS technology, to enable a new design approach for peripheral circuits in 3D NAND. Based on silicon data from a 3-WL GAA transistor, our TCAD simulations predict that a 24-layer stacked vertical-channel GAA transistor (with an effective channel length of ~1.2 μm in the vertical direction) can achieve a junction breakdown voltage exceeding 20 V, while maintaining sufficient ON-current drivability for WL setup operations. Additionally, incorporating approximately four dummy gates near the drain side as auxiliary gates (AG > 0 V) effectively mitigates GIDL-induced breakdown during the OFF state (Gate = 0 V). This paper outlines the layout design concept and provides device guidelines to enable efficient WL driver designs for the upcoming 1000-layer 3D NAND era.