Analog In-Memory-Compute with Multi-bit Silicon Ferro FinFET Array for Improved Energy and Area Efficiency

In this work, we demonstrate an analog in-memory-compute (AIMC) using single-transistor (1T) Ferro (FE) FinFET-based multiply-compute element (MCE). The fabricated MCE has a small cell size of 8F<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with 2bit per cell weight storage, a large memory window of 1.8V and a linear operation range of 1.2V. We experimentally demonstrate multiply-accumulation (MAC) operation at the array level with a program/erase inhibition biasing scheme. The 1T FE-FinFET based AIMC is achieves an area efficiency of 1377 TOPs/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> due to small cell size and multi-level-cell operation, and an energy efficiency of 697 TOPs/W enabled by low bit-line read voltage and excellent device linearity, with close to baseline computational accuracy.