Dynamic Flash Memory Operation Experimentally Validated with 65nm SOI Technology
Dynamic Flash Memory (DFM) have been fabricated on 300 mm SOI wafers with 65 nm technology, experimentally validating a wide "1" and "0" margin for the first time. The proposed device operates exclusively with positive polarity signals, eliminating the need for negative voltages. Thanks to its unique split-gate structure, a long retention time of over 10 seconds at 85 ℃, and a robust Bit Line (BL) disturbance time of 10 ms with the BL stress voltage (VSBL) of 2.5 V are demonstrated.
Authors
- Eyüp Can Demir (ORCID: https://orcid.org/0000-0003-4121-0699)
- Yisuo Li (ORCID: https://orcid.org/0009-0000-0497-4302)
- Yiqun Wan
- A. Fantini (ORCID: https://orcid.org/0000-0002-3220-8856)
- Christophe Lorant (ORCID: https://orcid.org/0000-0001-7363-9348)
- M. Kakumu
- I. Kunishima
- Koji Sakui (ORCID: https://orcid.org/0000-0003-2086-4802)
- Daniele Garbin (ORCID: https://orcid.org/0000-0002-5884-1043)
- K. Kanazawa
- Gautam Gaddemane (ORCID: https://orcid.org/0000-0003-0067-8674)
- Yoshihisa Iwata
- Nozomu Harada
Institutions
- IMEC (BE)
Publication Details
- Published
- 2025-05-18
- DOI
- https://doi.org/10.1109/imw61990.2025.11026959
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00