High-parallel In-memory Data Sorting based on 40nm Analog RRAM Chip
In this paper, we implement Maxsort, a high-parallel in-memory data sorting architecture utilizing resistive random access memory (RRAM). The Maxsort architecture is deployed and experimentally validated on an 1Mb analog RRAM chip fabricated using a 40nm standard CMOS process. The results indicate a significant improvement in energy efficiency by 34 times compared to traditional CPU-based computing systems. This advancement is anticipated to lay the groundwork for efficient data analysis techniques in the big data era.
Authors
- Hailong Ji (ORCID: https://orcid.org/0000-0002-8667-9127)
- Qishen Wang (ORCID: https://orcid.org/0000-0002-4013-6426)
- Yuhang Yang (ORCID: https://orcid.org/0000-0003-3964-5052)
- Shanguo Huang (ORCID: https://orcid.org/0000-0002-0750-2340)
- Rui Hua Xie (ORCID: https://orcid.org/0000-0002-0177-4417)
- Jingwei Sun (ORCID: https://orcid.org/0000-0001-5098-1503)
- Yimao Cai (ORCID: https://orcid.org/0000-0002-6854-8211)
- Zhengyuan Zhai (ORCID: https://orcid.org/0000-0002-8154-1540)
- Lin Bao (ORCID: https://orcid.org/0000-0002-3146-6124)
- Zongwei Wang (ORCID: https://orcid.org/0000-0001-6297-2700)
- Hao Zhang (ORCID: https://orcid.org/0000-0003-3410-7829)
- Yuan Ji (ORCID: https://orcid.org/0000-0001-7524-2109)
- Haisu Zhang
Institutions
- Beijing University of Posts and Telecommunications (CN)
- Peking University (CN)
- State Key Laboratory of Information Photonics and Optical Communications
Publication Details
- Published
- 2025-05-18
- DOI
- https://doi.org/10.1109/imw61990.2025.11026962
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Beijing Nova Program
- Fundamental Research Funds for the Central Universities