Hole-Side Airgap Integration as Enabler for 3D NAND Flash Z-Pitch Scaling

We demonstrate for the first time a scalable airgap introduced from the memory hole region as a 3D NAND flash z-pitch scaling enabler. The proposed integration scheme successfully forms airgaps with controlled depth extension in between word lines, offering great potential for manufacturability and advancing storage density and performance. We show that the introduction of these airgaps in a 30nm z-pitch 3D NAND flash process flow effectively reduces WL-WL interference and has no observable impact on the programming operation. While single cell erase operation shows degradation with airgaps, the conventional "all cells erase" scheme is much less impacted. Comparable reliability performance is obtained for devices with and without airgaps. Our results suggest that airgaps can be a viable solution for extreme z-pitch scaling in future 3D NAND flash technologies.