Monolithic 3D Stackable DRAM Design with BEOL-Compatible Oxide Channel Access Transistor

Monolithic 3D stackable DRAM has emerged as a promising solution to extend the scaling for DRAM technology. The silicon access transistor channel length has limited scaling potential in a horizontal 1T1C configuration due to leakage current constraint. In this work, we propose a BEOL-compatible W-doped In<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> (IWO) channel field-effect transistor (FET) as an alternative access transistor for 3D DRAM, enabling further horizontal scaling. By integrating the IWO nanosheet FET process with a horizontal 1T1C 3D DRAM process, we demonstrate low leakage and improved memory bit density. Through TCAD simulations, we analyze parasitic effects, retention characteristics, and sense margins. The bank-level simulation results show that 128-layer IWO-based 3D DRAM achieves 1.7× higher bit density (Mb/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) than its silicon counterpart. Furthermore, we evaluate processing-in-memory (PIM) architecture by hybrid bonding of 3D DRAM on top of TPU-like accelerators for large language model (LLM), showing 3× throughput and 14× energy efficiency compared to contemporary GPU with 2.5D integrated HBM.