On-Chip Capacitors with Wall-Type Structure in 9th Generation 3D VNAND Flash Memory

Wall type capacitor manufactured by contact/line co-patterning dual damascene (D/D) process was developed to improve capacitance density (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf>) for the latest flash memory. In this paper, contact/line co-patterning limitation related with capacitance, and D/D process issues of wall type capacitance were discussed. By employing the wall type capacitor, C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> value was increased by 47% with compare to the conventional line trench capacitor, resulting in opportunity of reducing 32% pump capacitor area. In next generation of flash memory including bonding VNAND, further advanced on-chip capacitors having reliable process and high C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf> have been required. Therefore, ideal scheme for the wall type structure was suggested, and candidates for future capacitor briefly mentioned