First Demonstration of Threshold Voltage Modeling in Multi-Hole V-NAND Flash Architecture with Noncircular Channel Hole Profiles

A predictive 3D parasitic capacitance modeling for multi-hole 3D vertical NAND (V-NAND) is first suggested to reflect geometric variations in mold height, dielectric thickness, critical dimension, hole pitch, and hole-to-cut variation due to the wordline cut (WLC) edge roughness. To parametrize channel hole profiles, various physical elements with respect to cell dimensions were extracted through metrological inspections, leading to the successful construction of a noncircular channel characterization model. Furthermore, we classified the contribution rates of physical elements to the threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) distribution mismatch depending on the channel hole location. Finally, a process design guideline was proposed to mitigate the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> distribution mismatch between the inner and outer channel holes. The proposed model can be used to predict cell characteristic variations of outer holes and optimize process parameters and layout designs to mitigate problematic mismatches between inner and outer channel holes.