Proposal of Block Erase and Verify Schemes for Ferroelectric NAND: Overcoming Critical Challenges from Threshold Voltage Polarity

As 3D NAND flash memory faces challenges, ferroelectric (FE) NAND has gained interest for its fabrication process compatibility and analogous operation mechanisms to charge-trap-flash (CTF) NAND. While recent advancements have demonstrated ferroelectric field-effect-transistor (FEFET) cells with large MWs and feasible reliability from the industry and academia, we point out that FE NAND faces critical challenges at the array level. Specifically, erase verify at the block level is challenging in FE NAND due to the opposite threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) polarity compared to in CTF NAND. This crucially hinders the feasibility of FE NAND for future 3D NAND technology. To overcome this, we propose viable write and erase verify schemes for the first time. The feasibility of the proposed schemes is demonstrated using fabricated cells with superior cell performances.