Enhancing 3D XPT/SOM Reliability: Strategies for Mitigating Spike Current and Improving Read Endurance

An optimized solution for read endurance in OTS-PCM chips is proposed to fulfill the need for the memory hierarchy. A significant increase in error rates was observed after cycling prior to optimization, prompting failure analysis. Selenium migration and GST-OTS intermixing are key failure modes identified by TEM analysis, causing either low-threshold or shorted voltage cells. Simulations showed that BL/WL capacitance reduced OTS spike current during the turn-on process, effectively reducing the primary failure mode found in the failed cells. Optimizing critical dimensions and the total resistance of the devices was proved to improve read endurance by reducing spike current duration, lowering the failure rate from 9% to 0.02%. Furthermore, memory redundancy is incorporated into design to ensure higher failure and error bit tolerance for normal functionality. These solutions are applicable and scalable to SOM and other XPT architecture memory technologies.