Accurate off-current evaluation by parasitic capacitance extraction in capacitor-less DRAM cells

We enable the accurate extraction of the off-current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf>) values in capacitor-less 2-transistor (2T0C) DRAM cells by developing two experimental methods for assessing the parasitic capacitance (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</inf>). We thus consider the total storage node capacitance (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tot</inf> = C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxRtr</inf> + C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">para</inf>) instead of the conventional gate capacitance of the read transistor (C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxRtr</inf>) for the extraction of I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf>. The application of these methods to our fabricated IGZO-based 2T0C devices reveals that the correction factor C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tot</inf>/C<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">oxRtr</inf> can be more than ten for scaled devices. This is corroborated with simulations for parasitic extraction and subthreshold leakage analysis. Even after applying this correction, our IGZO thin film transistors achieve I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</inf>/W < 5 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> off A/µm in 2T0C devices.