CTGAN-Bandit: A Conditional Tabular GAN Model Leveraging Upper Confidence Bound Estimators for Hardware Design Verification

Constrained Random Verification (CRV) is the de facto standard in ASIC design flow. Parametrized tests are simulated to exercise different execution paths of a Design Under Tests (DUT). These tests are simulated multiple times to generate different test scenarios, by leveraging constrained random stimulus generation. In this work, we propose a methodology utilizing Conditional Tabular Generative Adversarial Network (CTGAN) methodology, conditioned by Upper Confidence Bound (UCB) acquisition function as a reward. The combination of CTGAN and UCB allows the selection of the most relevant test parameters to efficiently navigate the test space and generate new tests. Our methodology, evaluated in live industrial projects, is able to generate new tests, and achieve higher coverage with respect to the baseline generated from the test suite manually created by experienced DV engineers, resulting in an overall coverage improvement of 2.3%.