Sample Preparation to Access Interposer Interconnects of Advanced Packaging for Probing

The increasing adoption of System-in-Package (SiP) devices in critical applications has raised concerns about security vulnerabilities in advanced packaging. The complexity of heterogeneous integration (HI) and 3D architectures exposes critical communication pathways, making them prime targets for adversaries. Traditional inspection methods struggle to identify and expose asset pathways within a package located in deeply embedded structures. In this work, we employ high-resolution X-ray microscopy (XRM) as a non-destructive approach to examine interposer layers, particularly between graphics processing unit (GPU) and high-bandwidth memory (HBM). After identifying regions of interest based on this preliminary scan, we use microwave-induced plasma (MIP) etching to selectively expose interconnects while preserving structural integrity. Focused ion beam (FIB) and scanning electron microscopy (SEM) was used to further enable precise delayering and detailed analysis of interconnect vulnerabilities. This integrated workflow demonstrates how nano-probing attacks in SiP devices can potentially compromise data confidentiality. Our findings highlight the need for robust security measures in advanced packaging architectures.