Low Cost ‘On Pitch Select Gate’ (OPS) Technology for 3D Flash Memory
Contrary to the general perception of 3D flash memory technology nodes being defined by the vertical stacking of word line layers, we, for the first time, present an unconventional approach employed in the mass production of BiCS FLASH™ generation 8 3D flash technology for achieving ~20% increase in bit density primarily with the help of the novel "on pitch select gate" (OPS) technology. This technology relies on cutting several functional select gate drain (SGD) transistors into semi-circular (SC) shapes to achieve lateral scaling. We also discuss some of the major engineering challenges encountered while realizing OPS, and the countermeasures employed to make OPS technology a reality, thereby creating a new path for the future of 3D flash memory industry.
Authors
- Manabu Hayashi (ORCID: https://orcid.org/0000-0002-2213-3918)
- Y. Shiino (ORCID: https://orcid.org/0000-0001-8534-0941)
- Amrit Prakash
- Sayako Nagamine
- Junhai Kai
- Takayuki Inoue
- Yutaka Ohira (ORCID: https://orcid.org/0000-0002-2387-0151)
- Debasree Dutta (ORCID: https://orcid.org/0000-0003-2745-9180)
- M. Higashitani
- Megumi Ishiduki
- Yoshiki Minemura
- Satoshi Shimizu (ORCID: https://orcid.org/0000-0001-8363-564X)
- H. Tomiie
- Kohki Okabe (ORCID: https://orcid.org/0000-0001-7627-7370)
- Yang Xiang (ORCID: https://orcid.org/0000-0003-0091-6935)
- Xiaochen Zhu
- Shuichi Miyazaki (ORCID: https://orcid.org/0000-0003-0369-1970)
- Shinji Murai (ORCID: https://orcid.org/0000-0003-3476-444X)
- Guirong Liang
- Shinji Suzuki (ORCID: https://orcid.org/0000-0003-3628-5952)
- H.W. Chin
- Takeshi Sakaguchi
- S. Yada
- Kazuki Isozumi
Publication Details
- Published
- 2025-05-18
- DOI
- https://doi.org/10.1109/imw61990.2025.11026986
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.73