Programmable architecture for offloading PDCP on FPGA-Capable SmartNIC

Packet Data Convergence Protocol (PDCP) is part of L2 Radio Protocol Stack in the LTE/5G air interface on top of the Radio Link Control (RLC) layer. PDCP layer provides cryptography and maintenance of sequence number in both transmit and receive directions. Reliable transmission and duplication are services provided in transmit direction. Reordering, in-order delivery and duplicate discard are receiving side services. Such complex requirements lead to CPU based programmable implementation suffering from high and/or indeterministic latency and high core counts. Conversely, proprietary low latency and/or high throughput systems don’t provide programmability and flexibility. We propose a system architecture consisting of P4 programmable packet processing pipelines inter-working with reusable externs with flexible interfaces. By meticulously redesigning the algorithms for both receive and transmit operations and adapting them to our architecture for user plane packets, we have developed 100Gbps/40MPPS software programmable PDCP on single FPGA-enabled SmartNIC, achieving average latency of 1.56 microseconds. Such a system meets best of both the worlds where we meet low latency and high throughput requirements without loss of programmability. The architecture is extended to accelerate other layers of the 5G radio stack. This architecture also gives the flexibility of generating telemetry data needed for integration of evolving AI/ML technologies.