System Verification and FPGA Implementation of Hardware Preemptive Scheduler for RISC-V Processor

In soft-core processor implementations based on software schedulers, there is an overhead that should not be neglected in HARD and FIRM real-time systems (RTS). Due to interrupt service routines (ISRs), which are asynchronous with the processor and have a higher priority than thread execution, the response time of an execution thread interrupted by an asynchronous ISR may exhibit jitter. The overall purpose of this paper is to present the hardware scheduler accelerator (HwSA) concept based on the RISC-V 4-stage pipeline CPU, where the scheduling algorithm is implemented in hardware. Assigning external events to execution threads, allows the application manager to improve the CPU execution behavior. Based on the multiplication of resources in the processor datapath, the pipeline registers store information for each thread. Switching thread contexts in the proposed soft-core CPU does not require more than 1-2 clock cycles. The proposed system is compared with existing soft-core processors using different parameters, such as the field-programmable gate arrays (FPGA) resources used for implementation, frequency, instruction set architecture (ISA), scheduler type, and the number of pipeline stages. The scientific contribution within this project is given by a dynamic scheduling algorithm implemented in hardware, support for resolving the priority inversion situations and the use of RISC-V ISA provided under open source licenses. The analysis shows that the proposed system has higher performance in terms of the event response time and lower jitter for the scheduler, as well as higher FPGA resource utilization compared to existing designs. The results obtained achieve the proposed objectives since the execution threads have their hardware context, mainly following the real-time deterministic response of the system.