Enhancing <scp>VLSI</scp> Design Efficiency With <scp>ML</scp>‐Based C‐<scp>ANN</scp>: Performance Optimization of Gate‐Stacked Ferroelectric <scp>FE</scp>‐<scp>MOSFETs</scp> for High‐Speed and <scp>RF</scp> Applications

ABSTRACT This study presents an innovative approach leveraging TCAD simulations and a Convolutional Artificial Neural Network (C‐ANN) to address challenges in VLSI design. A statistical sample of 4000 distinct values was simulated to predict drain current ( I ds ), achieving a dramatic reduction in runtime from 46 to 48 days (conventional TCAD) to just 100–120 s using the proposed ML‐based C‐ANN. The proposed gate‐stacking SiO 2 + HfO 2 FE‐MOSFET device demonstrates significant advancements, including reductions in short‐channel effects (SCEs), subthreshold swing (SS) by 3.12%–4.04%, and drain‐induced barrier lowering (DIBL) by 10.19%. Enhanced performance metrics include 52.95% higher I ON , 90% reduced gate leakage, and improved transconductance g m , transconductance generation function (TGF), early voltage ( V EA ), and intrinsic gain ( A v ) by 26.18%, 27.12%, 29.35%, and 101.24%, respectively. RF parameters such as gate capacitance ( C gg ), unity gain frequency ( f t ), and gain frequency product (GFP) improved by 34.53%, 48.74%, and 21.18%, making this device ideal for high‐speed switching and RF applications, promoting efficiency in low‐power VLSI designs.