Fully utilized pilot-aided digital signal processing with state pruning MLSD assisted adaptive symbol detection for symbol-rate sampling coherent optical interconnects

In high-speed coherent optical interconnects, symbol-rate sampling serves as a critical strategy for reducing digital signal processing (DSP) power consumption, yet its implementation faces significant challenges due to the sensitivity to analog-to-digital converter (ADC) sampling phase error and signal degradation under Nyquist constraints. This paper presents a hardware-efficient DSP architecture for FTN-shaped 16QAM systems that fully exploits pilot-aided processing to enable power-efficient, symbol-rate sampled coherent optical interconnects. The proposed design features a polarization-joint misaligned pilot scheme for enhanced carrier recovery (CR) and a pilot-aided adaptive symbol detection framework (PA-SDF) with state pruning MLSD. The PA-SDF dynamically switches between single-symbol (SSD) and multi-symbol detection (MSD) via a predefined mode-switching decision metric (MSDM), achieving an optimal BER-complexity trade-off. Experimental results at 80/90/100 Gbaud demonstrate a 0.7 dB receiver sensitivity improvement, while the proposed carrier recovery scheme reduces multiplier and adder usage by over 95%. Furthermore, the decoding architecture achieves a remarkable reduction in MLSD complexity to just 7.72% of conventional approaches, with 74% of symbols being processed through low-complexity SSD. The proposed fully utilized pilot-aided symbol-rate sampling DSP architecture presents a viable solution for next-generation, power-constrained data centers.